The present invention relates to a packet switching system.
In a packet switching system having a packet transmission controller, connected to a line group, for controlling packet transmission, and a packet switching unit for switching a data packet input through the packet transmission controller, the conventional packet switching unit comprises a general-purpose processor. The packet switching unit stores a received data packet in a common packet storage area in a main memory under the control of the processor, and performs switching and flow control. Input and output ports for the packet transmission controller are connected to a system bus together with the main memory and a direct memory access channel. Such a packet switching system is disclosed in U.S. Pat. No. 4,494,230 (Jan. 15, 1985). The data packet consists of a header part and a data part. In particular, during switching and flow control of the data packet, the header part must be directly processed by the processor. In the conventional packet switching unit, the main memory of the processor also serves as a packet path and a switch. For this reason, although the length of the header part to be processed by the processor is sufficiently shorter than the total length of the data packet, all the received packet data must be stored in the main memory. Therefore, it is difficult to obtain a storage area enough to achieve large-capacity, high-speed packet switching.